ARM TrustZone

ARM

7 execution modes

Secure/NonSecure State

Monitor mode

vector base register  ->

To provide the exception behavior described above, a TrustZone-enabled processor implements three sets of exception vector tables. One of these tables is for the Normal world, one is for the Secure world, and the other is for Monitor mode.

If high vectors are enabled ie, v bit is set in CP15 , then it jumps to 0xFFFF0000 despite the value of VBAR. This is for Secure/Non-Secure state. For monitor mode , VBAR is the base.