ARM Address Translation

page faults should not occur in the kernel address space.
ie, pages should be allocated from the memory manager before trying to use it.

32 bit virtual address

Name Level Page Table Page Size No. of
Size(KB) Supported(KB) Entries

Master/section level 1 16 1024 4096
Fine level 2 4 1, 4, or 64 1024
Coarse level 2 1 4 or 64 256

Level 1 :

PTBR 1 has the Page Table Base Register
bit 31-20 are used to index into the page table.
If last two bits(bit1 , bit0) in the corresponding entry of the first level page table are 10 which implies 1 MB pages are used.
12 bit base is taken from the first level pagetable and appended with 20 bit offset
from the virtual address to obtain the physical address.
bits 5- 8 indicate Domain
bit 2 - B bit
bit 3 - C bit
bit 10-12 AP

If last two bits are 00 , fault is generated.

If 01 , 11 then two level page tables are used.
bits 5- 8 indicate Domain

If 01 , coarse page table is used.
In first level page table entry , bits 31-10 are used as base for the second level page table.

Level 2:

Using the virtual address , corresponding entry in the second level page table is taken.
In that entry  , if bits 1,0 are
1. 01 -> large page(64k)
bits 31-16 are the base address of the physical page
11-4 are the access permissons fine grained to 16 KB.
3 - C Bit
2 - B bit
bits 19-16 of the virtual address are used to index into page table.
2. 10 -> small page(4k)
bits 31-12 are the base address of the physical page
11-4 are the access permissons fine grained to 16 KB.
3 - C Bit
2 - B bit
bits 19-12 of the virtual address are used to index into page table.
3. 11 -> tiny page(1k)
bits 31-10 are the base address of the physical page
5-4 are the access permissons fine grained to 16 KB.
3 - C Bit
2 - B bit
bits 19-10 of the virtual address are used to index into page table.
4. 00 -> page fault