ARM Features

Each core has the following features:
 ARM v7 CPU at 600 MHz
 32 KB of L1 instruction CACHE with parity check
 32 KB of L1 data CACHE with parity check
 Embedded FPU for single and double data precision scalar floating-point operations
 Memory management unit (MMU)
 ARM, Thumb2 and Thumb2-EE instruction set support
 TrustZone© security extension
 Program Trace Macrocell and CoreSight© component for software debug
 JTAG interface
 AMBA© 3 AXI 64-bit interface
 32-bit timer with 8-bit prescaler
 Internal watchdog (working also as timer)


The dual core configuration is completed by a common set of components:
 Snoop control unit (SCU) to manage inter-process communication, cache-2-cache and
system memory transfer, cache coherency
 Generic interrupt control (GIC) unit configured to support 128 independent interrupt
sources with software configurable priority and routing between the two cores
 64-bit global timer with 8-bit prescaler
 Asynchronous accelerator coherency port (ACP)
 Parity support to detect internal memory failures during runtime
 512 KB of unified 8-way set associative L2 cache with support for parity check and
ECC
 L2 Cache controller based on PL310 IP released by ARM
 Dual 64-bit AMBA 3 AXI interface with possible filtering on the second one to use a
single port for DDR memory access


TEX[2:0] C B Description
000 0 0 Strongly ordered
000 0 1 Shareable device
000 1 0 Outer and inner write-through, no write-allocate
000 1 1 Outer and inner write-back, no write-allocate
001 0 0 Outer and inner non-cacheable
001 0 1 Reserved
001 1 0 IMPLEMENTATION DEFINED
001 1 1 Outer and inner write-back, write-allocate
010 0 0 Non-shareable device
010 0 1 Reserved
010 1 - Reserved
011 - - Reserved
1BB A A Cacheable memory; outer = AA, inner = BB


AA/BB Attribute
00 Non-cacheable
01 Write-back, write-allocate
10 Write-through, no write-allocate
11 Write-back, no write-allocate